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http://ieeexplore.ieee.org/Xplore/lo...0/00176713.pdf
Transistor-level CMOS gate models for timing analysis andsimulation
Rumin, N.C.; Dagenais, M.; Zhang, W.
Circuits and Systems, 1991., IEEE International Sympoisum on
Volume , Issue , 11-14 Jun 1991 Page(s):2156 - 2159 vol.4
Digital Object Identifier 10.1109/ISCAS.1991.176713

http://ieeexplore.ieee.org/xpl/freea...unt=10&index=5
A Switch-Level Model and Simulator for MOS Digital Systems
Bryant, R.E.
Department of Computer Science, 256-80, California Institute of Technology;
This paper appears in: Computers, IEEE Transactions on
Publication Date: Feb. 1984
Volume: C-33, Issue: 2
On page(s): 160-177
ISSN: 0018-9340
Digital Object Identifier: 10.1109/TC.1984.1676408
Posted online: 2006-08-21 07:23:17.0